Cmos image sensor with test logic circuit for verifying operations thereof and method for testing th

专利摘要:
The CMOS image sensor of the present invention comprises: control and external system interface means for controlling the overall operation of the image sensor using a state machine and serving as an interface to an external system; A pixel array for arranging pixels for generating an electrical signal responsive to light and sensing information about an incoming image from the outside; An analog-digital conversion means for converting the analog voltage sensed by each pixel into a digital voltage for processing in a digital system; And a diagnostic logic circuit for diagnosing whether the control and external system interface means and the analog-to-digital converting means operate normally.
公开号:KR19990073016A
申请号:KR1019990006727
申请日:1999-03-02
公开日:1999-09-27
发明作者:권오봉；이석중；황규태；우드워드양
申请人:김영환；현대전자산업 주식회사；
IPC主号:

专利说明:

CMOS IMAGE SENSOR WITH TEST LOGIC CIRCUIT FOR VERIFYING OPERATIONS THEREOF AND METHOD FOR TESTING THE SAME}
The present invention relates to an image display apparatus using an image sensor implemented by a complementary metal oxide semiconductor (CMOS), and in particular, a CMOS image having a self-diagnosis function capable of determining normal operation between a memory and other components. A sensor and a diagnostic method thereof.
In general, an image sensor refers to a device that captures an image by using a property of a semiconductor that reacts to light. Each part of each subject in the natural world has a different electrical value at each pixel of the sensing device because the brightness and wavelength of the light are different from each other. That's what analog-to-digital converters do.
Conventional image display devices implemented with charge coupled devices (hereinafter referred to as CCDs) require a relatively high power supply (about 12V), and also require many process steps to implement charge coupled devices. do. In addition, since the sensor implemented by the CCD outputs an analog signal, a separate logic for converting the signal into a digital signal is required. However, the sensor process and the separate logic process are different from each other, so it is difficult to implement a single chip.
The present invention devised to solve the above problems is to provide a CMOS image sensor capable of driving at low power.
In addition, an object of the present invention is to provide a CMOS image sensor that can increase the degree of integration and increase the image data processing speed by implementing all the circuits necessary for image sensing in one chip.
Another object of the present invention is to provide a CMOS image sensor and a diagnostic method including a diagnostic logic circuit capable of verifying an operation state of each component.
1 is a block diagram of a CMOS image sensor of the present invention.
2 is an internal configuration diagram of a control and external system interface unit.
3 is a core block diagram of an image sensor.
4 is a conceptual diagram for the operation of the comparison unit and the double buffer.
5 is a CDS timing diagram.
6 is a latch array configuration diagram.
7 is a schematic diagram of a double buffer;
8 is a conceptual diagram for a mode register.
9 illustrates comparator inputs in diagnostic B mode and diagnostic C mode.
10 shows an FSM for diagnostic B mode and diagnostic C mode.
11 is a conceptual diagram of the operation of the comparison unit and the double buffer in the diagnostic C mode.
* Explanation of symbols for the main parts of the drawings
10: control and external system interface part
20: pixel array unit
30: Single Slope Analog-to-Digital Converter
40: double buffer
50: diagnostic logic department
The CMOS image sensor of the present invention for achieving the above object comprises a control and external system interface means for controlling the overall operation of the image sensor using a state machine, and serves as an interface to the external system; A pixel array for arranging pixels for generating an electrical signal responsive to light and sensing information about an incoming image from the outside; An analog-digital conversion means for converting the analog voltage sensed by each pixel into a digital voltage for processing in a digital system; And a diagnostic logic circuit for diagnosing whether the control and external system interface means and the analog-to-digital converting means operate normally.
The present invention also provides a CMOS image sensor having a pixel array that senses an image and outputs a sensed analog signal, wherein the CMOS image sensor controls an overall operation of the analog-to-digital converter and the CMOS image sensor. And a circuit comprising: a voltage generator for generating a first reference voltage, a comparator for comparing the reference voltage with a voltage from a pixel, and storage means for storing a digital value corresponding to the comparison result; The diagnostic logic circuit controls the comparator such that the comparator further generates a second reference voltage and a verification voltage according to a diagnostic mode of a mode register embedded in the CMOS image sensor, and the comparator corresponds to a comparison result. The storage means may be controlled by generating a write enable signal.
In addition, the present invention includes a pixel array for sensing an image and outputting a sensed analog signal; A voltage generator for generating a reference voltage; A comparator for comparing the reference voltage with a voltage from a pixel; Latch means for storing a digital value and an offset value corresponding to the comparison result; And a diagnostic logic circuit capable of determining an error of the analog-to-digital conversion, wherein the error diagnosis method of the CMOS image sensor comprises the verification voltage and the reference voltage generated from the voltage generator under control of the diagnostic logic circuit. A first step of comparing; A second step of storing a digital value corresponding to the comparison result in the latch means; And a third step of confirming a digital value stored in the latch means.
Furthermore, the present invention provides a pixel array for sensing an image and outputting a sensed analog signal; A voltage generator for generating a reference voltage; A comparator for comparing the reference voltage with a voltage from a pixel; Latch means for storing a digital value and an offset value corresponding to the comparison result; And a diagnostic logic circuit capable of determining an error of the analog-to-digital conversion, wherein the error diagnosis method of the CMOS image sensor comprises the verification voltage and the reference voltage generated from the voltage generator under control of the diagnostic logic circuit. A first step of comparing; A second step of storing, in the latch means, a predetermined digital value programmed in response to the comparison result; And a third step of outputting the digital value stored in the latching means and confirming whether the digital value is the same as the programmed digital value.
Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
1 shows a block diagram of a CMOS image sensor for processing signals sensed in a CMOS image sensor array of the present invention.
The CMOS image sensor according to the present invention includes a control and external system interface unit 10, a pixel array unit 20 composed of CMOS image sensing elements, a single slope analog-digital converter 30, and the converter. It consists of a diagnostic logic unit 50 that can check whether it is operating normally. In addition, the single slope analog-to-digital converter 30 compares an analog signal from the lamp voltage generator 31 and the pixel array unit 20 to generate a lamp voltage for a reference voltage and a verification voltage with the lamp voltage. Comparator 32 and a double buffer 40 for storing the comparison result as an encoded digital value.
In more detail, the control and external system interface unit 10 uses an finite state machine (FSM) for integration time, scan address, operation mode, and frame rate. The overall configuration of the image sensor, such as a bank, a clock division, and the like, and serves as an interface to an external system, is illustrated in FIG. 2.
The pixel array unit 20 is composed of NxM unit pixels made to maximize a property of responding to light to sense information about an image coming from the outside, the unit pixel is a photodiode, transfer ( transfer transistor, reset transistor, and select transistor.
The single slope analog-to-digital converter 30 performs a function of converting an analog signal sensed by the pixel array unit 20 into a digital signal. In the present invention, a digital signal is generated by comparing a ramp voltage with the analog signal. I'm using the method. As the ramp voltage falls from the ramp voltage generator 31 with a predetermined slope, it finds a point coinciding with the pixel voltage from the pixel array. In addition, when the ramp voltage is generated and starts to fall, the control and external system interface unit 10 generates a count signal to count the degree of fall. For example, if the ramp voltage falls and coincides with the pixel voltage at the 20th clock, the digital value for the analog pixel voltage is 20. In this way, the digital value at the coincidence time of the two voltages is stored in the double buffer 40. The setting of such digital values will be described in detail in FIG.
In addition, the CMOS image sensor according to the present invention further comprises a diagnostic logic unit 50 inside the chip to easily detect whether there is a malfunction that may occur in setting the digital value.
FIG. 2 is an internal configuration diagram of the control and external system interface unit 10, and has a plurality of configuration registers 60 directly programmable by a user, so that programs related to various internal operations may be programmed. It is possible to control the operation of the entire chip in accordance with this programmed information. The operation of the image sensor is programmed through an inter integrated circuit (IIC) bus interface, which is controlled by a driver 70 for driving the image sensor, for example, a field programmable gate array (FPGA) 80. When the program information is transmitted through the IIC control block 90, which receives the data input via the bus IIC in synchronization with the clock SCK, the IIC control block 90 interprets the input information according to the IIC bus protocol and the batch register 60 ) To control.
The program between the driver 70 and the image sensor is made through the batch register 60, which can be read and written at any time. This programmed information is internally updated frame by frame, and this is done through a special register called the shadow register 100. The shadow register 100 has a high value of the ENB signal (a signal applied from the outside), which is a sensor enable signal that specifies the operation of the image sensor, or has a high value, or at the beginning of every frame, to the batch register 60. The contents of the batch register are copied only when there is updated information, and the information stored in the registers in units of screens is affected. In addition, the shadow register 100 may prevent the screen from being temporarily broken due to interruption or change of a user command.
The information contained in the shadow register 100 indicates the overall operation of the image currently being output. A basic information register for storing information related to the size and version of the image sensor, an operation mode register for specifying an operation mode, and a row Window control registers to store (Row) and column start addresses, window size and window width, blank period of horizontal synchronization signal (HSYNC), blank of vertical synchronization signal (VSYNC) Period, charge integration time of the photodiode, the frame rate adjustment register that specifies the clock distribution ratio, reset level specification, and gain for each color (red, green, blue). It consists of an adjustment register to adjust.
The main control unit 110 controls each component of the image sensor according to the information contained in the shadow register 100, and the address generation unit 120 controls the pixel array unit 20 and the double buffer. An address of 40 is generated.
3 is a core block diagram of an image sensor including a unit pixel 200, one comparator 320, and a unit latch 400 constituting a double buffer. FIG. 3 shows the structure of a unit pixel. The unit pixel includes a photodiode 21 and four NMOS transistors M1, M2, M3, and M4, which generate electron and hole pairs in response to incident light. Becomes The charge generated in the photodiode 21 is transferred to the floating junction (FD) when the transfer transistor M1 is opened, and the transferred charge is represented by the voltage change of the floating junction by the formula "Q = CV". . The time when the transfer transistor M1 is closed becomes the charge integration time, which corresponds to the exposure time of the optical camera.
The reset transistor M2 is for correlated double sampling (hereinafter referred to as CDS). The reset transistor M2 is turned on and the transfer transistor M1 is turned off. When off, the floating junction is charged to the reset voltage. By reading the voltage of the floating junction at this time, a voltage corresponding to the reset level can be obtained. If the transfer transistor M1 is turned on while the reset transistor M2 is turned off, the charge generated in the photodiode 21 is transferred to the floating junction, and the voltage of the floating junction due to the transferred charge is transferred to the data level. Becomes Subtracting the voltage of the data level from the voltage of the reset level eliminates the offset in the pixel and voltage comparator 32, which is the basic concept of CDS. In other words, by removing the specific voltage inherent in each unit pixel from the data value, the voltage value of the pure image can be obtained.
FIG. 4 is a conceptual diagram of the operation of the comparator 32 and the double buffer 40, and shows an example of generating a digital value by comparing an analog voltage obtained from a pixel with a comparison reference voltage output from the ramp voltage generator 31. . Such analog-to-digital conversion can be accomplished by a variety of methods, but the present invention uses a single-slope method and consists of organic operation of the comparator 32 and the double buffer 40. When the voltage conversion operation starts, the ramp voltage generator 31 compares the pixel voltage obtained from the pixel by dropping the voltage by a predetermined step every clock. In addition, the initial value of the lamp voltage may be set to the expected maximum pixel voltage or individually set by the user. At this time, the control and external system interface unit 10 counts according to the clock, and counts the counting value at the time when the magnitude of the pixel voltage and the falling ramp voltage coincide in the double buffer 40. Make a change.
The unit latch 400 of FIG. 3 includes transistors M5 and M6 serving as four switches. Transistor M5 is turned on / off in response to the output of comparator 32, and transistor M6 is turned on / off by a bank select signal that selects one group of the double buffer of FIG. In the state where the corresponding buffer group is selected and the transistor M6 is turned on, if the reference voltage is greater than the pixel voltage, the transistor M5 is turned on. The value coming from the counter while the two transistors M5 and M6 are turned on turns on the capacitive transistor M7 to store data. The data stored in the transistor M7 is read into a single-ended bitline with precharge means via transistor M8 turned on by the column select signal.
On the other hand, when the reference voltage is smaller than the pixel voltage, since the transistor M5 is turned off, the count value can no longer be written to the latch 400, and thus the value written in the latch becomes the converted digital value. At this time, the counter exists in the control and external system interface unit 10, and the actual data used in the unit latch 400 is data converted through a code converter such as a gray code converter for efficient storage.
5 shows a CDS timing diagram for removing the offset. The first slope is for reading the voltage at the reset level, and the second is for reading the data level. Therefore, the configuration of the latch array also consists of two buffers, each of which has two banks for actually storing the digital value for the reset level and for storing the digital value for the data level. The configuration of the latch array for this is shown in FIG. In the case of the conventional analog double sampling, an offset caused by a newly added circuit is generated in the circuit structure, and the circuit design for signal processing is difficult. In the present invention, the analog image value is converted into a digital value at the reset level. Later, the method of subtracting the digital image value of the reset level from the digital value of the data level is used, thereby providing the ease of circuit design simplification.
FIG. 7 is a configuration diagram of a double buffer, in which an image signal value is stored in a double buffer, that is, a storage means through an analog-to-digital converter, and at the same time, it is necessary to output a digital data value for the immediately preceding image signal. Accordingly, the present invention implements a double buffer to realize a pipeline structure. CMOS image sensors with NxM pixel arrays that process 8-bit data require N comparators and Nx8X4 latch cells.
As described above, at least two line buffers are required to write the output value of the analog-to-digital converter to the storage means and to read out the stored values. This enables pipeline configuration at the architecture level. And because the data can be read asynchronously, the external interface is much more free, and data congestion on the communication channel is more convenient. In other words, when data is compressed, an asynchronous interface is absolutely required to efficiently control congestion in transmitting a variable amount of data such as a variable length code.
When reading the data in the line buffer, only even or odd numbers can be read. In some cases, data can be read while skipping various numbers such as 3 or 4 pixels, which is advantageous for subsampling and processing. Increasing the number of lines in the line buffer enables easy application of two-dimensional (dimension) image data blocks to various signal processing without using additional buffers. In particular, in the case of the present invention, the double buffer will be an essential element when used in combination with a parallel analog-to-digital converter.
The diagnostic logic unit 50 is not an essential component in the configuration of the image sensor, but has been applied to easily detect whether the image sensor is malfunctioning and to improve the verifyability.
To set the diagnostic mode, a mode setting register is placed in a batch register in the control and external system interface unit 10, and the operation mode is designated through this register. This register is designated through a programming interface. When a mode change occurs, the diagnostic logic unit 50 operates according to the change mode.
FIG. 8 illustrates a mode register. When the module is initialized, the mode register is in a normal mode, and three diagnostic modes are programmable by programming. The other three diagnostic modes of the present invention are to externally monitor the operating state of the state machine (FSM) of the control and external system interface unit, and to use the diagnostic A mode (used to determine whether the control logic and programming interface is malfunctioning). Test_A Mode), diagnostic B mode (mainly for diagnosing errors in the voltage comparator), and the need for help with a ramp voltage generator, and stuck-at faults for latch arrays in the double buffer section. -fault) is used to diagnose errors. There is a diagnostic C mode (Test_C Mode) that verifies errors by repeatedly writing and reading simple patterns.
The output of the diagnosis result is made through the data bus DATA [7: 0] of FIG. 1. In the normal operation mode, a value read from the sensor pixel is output to the data bus, but when the diagnostic mode is obtained, the result of the diagnostic mode and the pixel data are multiplexed, so there is no need to add a separate pin.
Diagnosis A mode (Test_A Mode) is a mode for checking the malfunction of the control and external system interface. Instead of outputting the digitized value of the sensor pixel through the data bus, the value of FSM, which plays a key role of the controller, Output Since the value of the FSM changes according to the state of the internal control logic and the state of the external control pin, monitoring the change in the value of the FSM enables diagnosis of malfunction.
Diagnostic B mode is primarily for testing comparators. As shown in FIG. 9, a comparator plays a key role in converting an analog voltage sensed by a pixel into a digital voltage.
In the present invention, as can be seen in Figure 9, instead of the unpredictable voltage coming from the pixel, both input voltages that enter the comparator in the diagnostic B mode operation are produced by the ramp voltage generator. The reference voltage is a ramp voltage that decreases linearly with the same clock as in the normal operation mode, and the test voltage is a predictable intentional fixed voltage for verifying whether the comparator is operating.
The FSM for the diagnostic B mode and the diagnostic C mode is shown in FIG. 10, and the operation is as follows.
-IDLE: status when not set to diagnostic B mode and diagnostic C mode,
-READY: Preparatory step for each verification in Diagnostic B mode and Diagnostic C mode, this time outputs the diagnosis number and sets the verification voltage through output pin DATA [7: 0],
-COMP: In the READY state, the voltage comparator writes data to the latch of the double buffer part by comparison according to the predetermined test voltage prepared in the READY state. In this case, the digital voltage corresponding to the verification voltage through DATA [7: 0] Output status,
-WAIT1: A state in which 00H is output indicating that the reset latch is compared through DATA [7: 0] in preparation for reading what has been written to the reset latch array that supports dual sampling (CDS).
-TEST1: The value corresponding to the reset latch is output through DATA [7: 0]. This value should be the same as the value output from the 'COMP' state.
-WAIT2: Signal indicating that the value of the 'actual data latch' is to be output next, and ffH is output through DATA [7: 0].
-TEST2: Outputs the value of 'actual data latch' through DATA [7: 0], and this value should be the same as the value output from 'COMP' state.
-LOOPB: Since the verification for a buffer has been completed, toggle the buffer (from buffer A to buffer B, and vice versa) and repeat the same cycle, and after verifying two buffers, change the verification voltage. After going back to the READY state and repeating the verification, the output value through DATA [7: 0] is 00H, and
-LOOPC: This is the status for diagnostic C mode. Toggles the buffer as in the LOOPB status and changes the value written to the latch as described in the Diagnostic C mode below when the two buffers are verified.
The verification voltage is for verifying the operation of the comparator, and the difference is made in a step of about 1/4 of the resolution of the comparator in consideration of the complexity of the circuit and the characteristics of the analog circuit which makes the verification voltage. Create a verify voltage with a resolution of bits.
The diagnostic C mode is mainly for checking latches in the 'double buffer section'. As shown in FIG. 7, in the buffer section, when N latch cells are formed in one line, each cell has 8 Because it has a bit value, a latch cell of (8x2x2xN) is required, and the larger the N, the greater the probability that an error will occur.
In normal operation, as shown in FIG. 4, the counter value of the result of comparing the analog voltage sensed by the pixel with the reference voltage is recorded in the latch of the double buffer part. Therefore, in the case of an error in the latch, the pixel, the comparator and the counter Can work incorrectly.
Diagnostic C mode, unlike Diagnostic B mode, is designed to detect errors that can occur in the latch, so it is hardwarely expensive to have a dedicated read / write interface on the 'double buffer section' latch. Therefore, in the present invention, the diagnosis C mode is performed by using all the normal operation modes or the diagnosis B methods.
As shown in FIG. 11, the verify voltage is set to any voltage that is less than the highest and greater than the lowest of the reference ramp voltage to provide a write enable signal to the latch. The latch write enable signal is then generated until the verify voltage is greater than the comparison reference voltage.
In normal operation mode or diagnostic B mode, the counter value is changed synchronously with the lamp voltage.In diagnostic C mode, instead of writing the counter output value, the following value is written to make it easier to detect stuck-at-fault. Write repeatedly until the Able signal turns off.
11111111
00000000
10101010
01010101
The value is changed to the next value after the mode verification to the buffer B in the state where the FSM of FIG. 10 is 'LOOPC'.
Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
The present invention made as described above can implement all the circuits required for image sensing in a single chip, can not only verify the operation of each circuit, but also has the effect of implementing a low-power drive image sensor.

权利要求:
Claims (31)
[1" claim-type="Currently amended] Control and external system interface means for controlling the overall operation of the image sensor using a state machine and serving as an interface to the external system;
A pixel array for arranging pixels for generating an electrical signal responsive to light and sensing information about an incoming image from the outside;
An analog-digital conversion means for converting the analog voltage sensed by each pixel into a digital voltage for processing in a digital system; And
And a diagnostic logic circuit for diagnosing whether the control and external system interface means and the analog-to-digital converting means operate normally.
[2" claim-type="Currently amended] The method of claim 1,
And said control and external system interface means comprise shadow registers that are not available to a user.
[3" claim-type="Currently amended] The method of claim 2,
Said control and external system interface means comprising a plurality of user-available batch registers, said shadow register having information of the batch registers currently being processed.
[4" claim-type="Currently amended] The method of claim 3,
The analog-digital conversion means,
A voltage generator generating a first reference voltage in a normal mode and a second reference voltage and a verification voltage in a test mode;
A comparator for receiving and comparing the sensed voltage from the pixel array with a first reference voltage from the voltage generator in a normal mode, and receiving and comparing the voltage generator second reference voltage and a verify voltage in a test mode; And
And storage means for storing a digital value corresponding to the comparison result.
[5" claim-type="Currently amended] The method of claim 4, wherein
The storage means has a double buffer for forming a pipeline structure, each buffer is divided into a first and a second group, the first group stores an offset value generated in the CMOS image sensor itself, and the second And the group stores data converted by the analog-digital converting means.
[6" claim-type="Currently amended] According to claim 4,
The diagnostic logic circuit,
In response to control and mode information from an external system interface means, controlling the output of said voltage generator.
[7" claim-type="Currently amended] The method of claim 4, wherein
The batch register includes a diagnostic mode register, and the diagnostic mode register includes:
First information for diagnosing a state machine of the control and external system interface means;
Second information for diagnosing an error of the comparator; And
And third information for diagnosing an error of said storage means.
[8" claim-type="Currently amended] The method of claim 4, wherein
The digital value is a coded count signal from the control and external system interface means.
[9" claim-type="Currently amended] The method of claim 4, wherein
And said storage means transfers data asynchronously to said control and external system interface means.
[10" claim-type="Currently amended] The method of claim 5,
The storage means includes a plurality of latch circuits,
The latch circuit,
A first transistor receiving the count signal in response to an output of the comparator;
A second transistor configured to transfer an output of the first transistor in response to a bank signal for selecting a group of the buffer;
A third transistor for storing a logic data value in response to an output of the second transistor; And
And a fourth transistor configured to transfer a data value stored in the third transistor to a bit line in response to a column select signal.
[11" claim-type="Currently amended] The method of claim 6,
The CMOS image sensor,
And a multiplexer for selectively controlling the output in the normal mode and the output in the test mode.
[12" claim-type="Currently amended] The method of claim 6,
And the pixel array has NxM pixels, the comparator has N OP amplifiers, and the storage means has 4x (number of bits to be processed) x N latch circuits.
[13" claim-type="Currently amended] The method of claim 3,
The shadow register is a CMOS image sensor, characterized in that by copying the information of the batch register in the screen unit.
[14" claim-type="Currently amended] A CMOS image sensor having a pixel array for sensing an image and outputting a sensed analog signal,
The CMOS image sensor includes an analog-to-digital converter and a diagnostic logic circuit for controlling the overall operation of the CMOS image sensor,
The analog to digital converter,
A voltage generator for generating a first reference voltage, a comparator for comparing the reference voltage with a voltage from the pixel, and storage means for storing a digital value corresponding to the comparison result;
The diagnostic logic circuit controls the comparator such that the comparator further generates a second reference voltage and a verification voltage according to a diagnostic mode of a mode register embedded in the CMOS image sensor, and the comparator writes corresponding to the comparison result. And generating an enable signal to control the storage means.
[15" claim-type="Currently amended] The method according to claim 14,
And said control and external system interface means comprise shadow registers that are not available to a user.
[16" claim-type="Currently amended] The method of claim 15,
Said control and external system interface means comprising a plurality of user-available batch registers, said shadow register having information of the batch registers currently being processed.
[17" claim-type="Currently amended] The method of claim 16,
The shadow register is a CMOS image sensor, characterized in that by copying the information of the batch register in the screen unit.
[18" claim-type="Currently amended] The method of claim 14,
And said CMOS image sensor comprises a multiplexer for selectively outputting image data from said pixel array and digital values of said diagnostic mode.
[19" claim-type="Currently amended] The method of claim 14,
The storage means,
It has a double buffer to form a pipeline structure, each buffer is divided into a first and a second group, the first group stores an offset value generated by the CMOS image sensor itself, the second group is the pixel CMOS image sensor, characterized in that for storing data from.
[20" claim-type="Currently amended] The method of claim 10,
The digital value is a coded count signal.
[21" claim-type="Currently amended] The method of claim 12,
The storage means includes a plurality of latch circuits,
The latch circuit,
A first transistor receiving the count signal in response to an output of the comparator;
A second transistor configured to transfer an output of the first transistor in response to a bank signal for selecting a group of the buffer;
A third transistor for storing a logic data value in response to an output of the second transistor; And
And a fourth transistor configured to transfer a data value stored in the third transistor to a bit line in response to a column select signal.
[22" claim-type="Currently amended] The method of claim 14,
And the pixel array has NxM pixels, the comparator has N OP amplifiers, and the storage means has 4x (number of bits to be processed) x N latch circuits.
[23" claim-type="Currently amended] The method of claim 4, wherein
And said storage means transfers data asynchronously to write, read and addressing circuitry.
[24" claim-type="Currently amended] A pixel array configured to sense an image and output a sensed analog signal; A voltage generator for generating a reference voltage; A comparator for comparing the reference voltage with a voltage from a pixel; Latch means for storing a digital value and an offset value corresponding to the comparison result; And a diagnostic logic circuit capable of determining the error of the analog-to-digital conversion.
A first step of comparing the verification voltage generated from the voltage generator with the reference voltage under control of the diagnostic logic circuit;
A second step of storing a digital value corresponding to the comparison result in the latch means; And
And a third step of checking a digital value stored in the latching means.
[25" claim-type="Currently amended] The method of claim 24,
The latching means has a double buffer for forming a pipeline structure, wherein each buffer is divided into a first group for storing the digital value and a second group for storing the offset value. Diagnostic method.
[26" claim-type="Currently amended] The method of claim 24,
The second step,
A fourth step of storing the digital value in the first group and outputting the digital value to a data output terminal of the CMOS image sensor; And
And storing the digital value in the second group and outputting the digital value to the data output terminal of the CMOS image sensor.
[27" claim-type="Currently amended] The method of claim 24,
And the method is performed at least once by changing the verification voltage.
[28" claim-type="Currently amended] A pixel array configured to sense an image and output a sensed analog signal; A voltage generator for generating a reference voltage; A comparator for comparing the reference voltage with a voltage from a pixel; Latch means for storing a digital value and an offset value corresponding to the comparison result; And a diagnostic logic circuit capable of determining the error of the analog-to-digital conversion.
A first step of comparing the verification voltage generated from the voltage generator with the reference voltage under control of the diagnostic logic circuit;
A second step of storing, in the latch means, a predetermined digital value programmed in response to the comparison result; And
And a third step of outputting the digital value stored in the latching means and confirming whether or not it is the same as the programmed digital value.
[29" claim-type="Currently amended] The method of claim 28,
The latching means has a double buffer for forming a pipeline structure, wherein each buffer is divided into a first group for storing the digital value and a second group for storing the offset value. Diagnostic method.
[30" claim-type="Currently amended] The method of claim 28,
The second step,
A fourth step of storing the digital value in the first group and outputting the digital value to a data output terminal of the CMOS image sensor; And
And storing the digital value in the second group and outputting the digital value to the data output terminal of the CMOS image sensor.
[31" claim-type="Currently amended] The method of claim 28,
And the method is performed at least once by changing the verification voltage.

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同族专利:

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公开号 | 公开日

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NL1011406A1|1999-09-01|

---

GB2334848A|1999-09-01|

---

GB9904591D0|1999-04-21|

---

US6633335B1|2003-10-14|

---

GB2334848B|2000-04-19|

---

KR100324592B1|2002-02-16|

---

DE19908858B4|2013-07-11|

---

TW414922B|2000-12-11|

---

FR2778049B1|2001-01-05|

---

NL1011406C2|2000-01-07|

---

JPH11331883A|1999-11-30|

---

DE19908858A1|1999-09-16|

---

JP4455686B2|2010-04-21|

---

FR2778049A1|1999-10-29|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1998-02-28|Priority to KR19980006686

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1998-02-28|Priority to KR1019980006686

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1999-03-02|Application filed by 김영환, 현대전자산업 주식회사

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1999-09-27|Publication of KR19990073016A

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2002-02-16|Application granted

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2002-02-16|Publication of KR100324592B1

优先权:

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申请号 | 申请日 | 专利标题

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KR19980006686|1998-02-28|

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KR1019980006686|1998-02-28|